Trigger mechanism for current acquisition used for motor control applications

ABSTRACT

A trigger mechanism for starting current acquisition for motor control applications is disclosed. The present invention may generate an edge (ADC trigger) that can be used to start current acquisition by the ADC. The present invention may reduce the overhead involved in synchronizing the current acquisition with PWM generation and also minimize the wait period for software conversions to complete by replacing software-based timing with a hardware-based trigger mechanism.

BACKGROUND OF THE INVENTION

The present invention relates to apparatus and methods for triggeringcurrent acquisition and, more particularly, to apparatus and methods fortriggering current acquisition used for motor control applications assoon as a valid state is detected on the motor drive.

Field oriented control of motor drive depends upon accurate and timelyacquisition of phase currents. Additionally, the currents need to beacquired at specific conditions of the motor drive. These conditions aregiven in terms of pulse width modulation (PWM) signals. The phasecurrent acquisition has to be initiated when all three PWM signals areeither at logic 0 (also known as a “000 condition”) or when all threeare at logic 1 (also known as a “111 condition”).

However, the pulse widths are variable among the three phases and theexact time when the acquisition needs to be started (logic 0 or logic 1)is difficult to determine. The existing implementations use centeraligned PWM waves and start the acquisition when the center time isreached at either logic 0 or logic 1.

This scheme has two major drawbacks. First, the time lost by notstarting the current acquisition at the instance the valid conditionoccurred has to be compensated by waiting for the conversion to completewhen reading the current back from the analog to digital converter(ADC). Second, the overhead of synchronizing with the center time of thePWM (usually done in software) also can eat away at real time usage.

The ADCs used to actually acquire the motor phase currents need to betriggered so that they can start the signal acquisition. Typically, thisis done using a software counter. In cases where a software timer (orcounter) can not be coupled with generating the PWM drive and triggeringthe acquisition, this scheme cannot be used.

As can be seen, there is a need for apparatus and methods for startingcurrent acquisition as soon as possible and for removing the overhead insynchronizing the center times so that the ADC can be triggered as soonas a valid state (000 or 111) is detected on the PWM drive.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a trigger mechanism for currentacquisition comprises an inverter generating pulse width modulation(PWM) signals for each phase of a motor; a trigger mechanism receivingthe PWM signals, the trigger mechanism including at least one controllogic for comparing the PWM signals and generating an output signal forat least one of the control logic, wherein when the output signal ishigh, the output signal is used to trigger current acquisition by ananalog to digital converter (ADC).

In another aspect of the present invention, a trigger mechanism forcurrent acquisition comprises an inverter generating three pulse widthmodulation (PWM) signals, one PWM signal for each of the three phases ofa motor; a trigger mechanism receiving the three PWM signals, thetrigger mechanism including an AND block and a NOR block, the AND blockgenerating a high output signal when each of the three PWM signals arein a logic 1 state, and the NOR block generating a high output signalwhen each of the three PWM signals are in a logic 0 state, wherein whenthe output signal is high, the output signal is used to trigger currentacquisition by an analog to digital converter (ADC).

In a further aspect of the present invention, a method for triggeringacquisition of phase currents for motor control comprises obtaining aPWM signal from each phase of the motor control; inputting each of thePWM signals to a control logic; and triggering current acquisition whenthe control logic generates a high signal for a predefined valid PWMstate.

These and other features, aspects and advantages of the presentinvention will become better understood with reference to the followingdrawings, description and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic drawing showing a motor control scheme using thetrigger mechanism of the present invention;

FIG. 2 is a schematic drawing showing the trigger acquisition controlblock of the present invention;

FIG. 3 is a schematic drawing showing circuits for detecting variousenergizing patterns according to an embodiment of the present invention;and

FIG. 4 describes a method for triggering acquisition of phase currentsfor motor control according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description is of the best currently contemplatedmodes of carrying out the invention. The description is not to be takenin a limiting sense, but is made merely for the purpose of illustratingthe general principles of the invention, since the scope of theinvention is best defined by the appended claims.

Various inventive features are described below that can each be usedindependently of one another or in combination with other features.However, any single inventive feature may not address any of theproblems discussed above or may only address one of the problemsdiscussed above. Further, one or more of the problems discussed abovemay not be fully addressed by any of the features described below.

Broadly, the present invention provides a trigger mechanism and relatedmethods for starting current acquisition for motor control applicationsas soon as possible and for removing the overhead in synchronizing thecenter times so that the ADC can be triggered as soon as a valid state(000 or 111) is detected on the PWM drive. The present invention maygenerate an edge (ADC trigger) that can be used to start currentacquisition by the ADC.

Unlike conventional current acquisition schemes, which may use softwareto determine a center time of a valid state and thereby preventing truereal time usage, the present invention may save the overhead involved insynchronizing the current acquisition with PWM generation and alsominimize the wait period for the prior art software conversions tocomplete.

Referring to FIG. 1, there is shown a schematic drawing of a motorcontrol scheme 10 using a trigger mechanism 12 according to the presentinvention. A motor 14 of the motor control scheme 10 may be, forexample, a three-phase permanent magnet synchronous motor. An inverter16 may be provided with a half bridge circuit 16a, 16b, 16c for each ofthe phases of power delivered to the motor 14. The inverter 16 maygenerate a pulse width modulation (PWM) signal 18 for each phase.

The motor control scheme may include a DC power supply 20 providingpower to the inverter 16 and a current detection circuit 22 for poweringon and off an analog to digital converter (ADC) 24 based on the presenceor absence of DC power.

The trigger mechanism 12, as described in greater detail below inreference to FIG. 2, may receive the PWM signals 18 from the inverter 16and generate an output 26 which may, depending on the PWM signals 18,turn on current acquisition by the ADC 24.

Referring now to FIG. 2, there is shown a schematic drawing of thetrigger mechanism 12 of the present invention. The PWM drive input maybe from the inverter 16, as described in FIG. 1. Each phase signal 18 a,18 b, 18 c of the PWM signal 18 may be provided to a control logic, suchas an AND block 30 and a NOR block 32. In this case, when the phasesignals 18 a, 18 b, 18 c are (1, 1, 1), a valid state (logic 1) may bedetected and the output from the AND block 30 may be high (also referredto as a “1” signal). In addition, when the phase signals 18 a, 18 b, 18c are (0, 0, 0), a valid state (logic 0) may be detected and the outputfrom the NOR block 32 may be “1”.

A multiplexer 34 may be provided with a mode input 36. The AND block 30output signal 30 a and the NOR block 32 output signal 32 a that may beprovided to the multiplexer 34 which may output one of these signals 30a, 32 a to an edge detector 40. The edge detector 40 may be a circuitknown in the art for changing a level input into an edge output forswitching a device. In this case, the level input may be (during a validstate), a “1” signal 38. The edge detector 40 may convert this level “1”signal 38 into an edge signal 42 for activating the ADC 24 (see FIG. 1).The multiplexer 34 may be a typical multiplexer integrated circuit (IC),such as a 7400 series IC, as is known in the art.

Another way of re-creating the motor phase currents, as isconventionally performed in the prior art, is to sample the DC currentdrawn by the motor at specific intervals such that only one motor phasecurrent is flowing. Thus, if the current at the DC power supply issampled at that particular instance, it would equal the motor phasecurrent. Typically, this method would involve a peripheral or modulethat is generating the PWM drive signals to initiate the currentacquisition. Thus, the peripheral will add to the overhead to generatethe trigger signal as well as the real time usage of the system.

A solution for the issues described in the above paragraph may be foundin the embodiment of the present invention as shown in FIG. 3. The ANDblock 30 and the NOR block 32 of FIG. 2 may be replaced by orsupplemented with blocks 1-6 (labeled 50, 52, 54, 56, 58 and 60,respectively), thus providing the multiplexer 34 with either 6 (ifreplaced by) or 8 (if supplemented with) inputs. In either event, themode input 36 may instruct the multiplexer 34 which input is of interestand to be delivered as the output 38.

Table 1 below shows the various inputs for each of the PWM signals 18 a,18 b, 18 c and which phase current may be detected by such an input. Forexample, if it was determined that the current in PWM C (18 c) was to bethe trigger (logic 0, 0, 1, wherein PWM C is the high (“H”) signal), thecircuit of block 50 may be used to generate a “1” output in such a case.If it was determined that the current in PWM B (18 b) was to be thetrigger (logic 0, 1, 0), the circuit of block 52 may be used to generatea “1” output. Finally, if it was determined that the current in PWM B(18 b) and in PWM C (18 c) was to be the trigger (logic 0, 1, 1; alsoreferred to as −PCM A), then the circuit of block 56 may be used togenerate a “1” output. As discussed above, the selection of which blockis used may be controlled with the mode input 36 of the multiplexer 34.

TABLE 1 Phase currents detected for various PWM inputs Phase current PWMA PWM B PWM C detected Block L L H PWM C Block 50 L H L PWM B Block 52 HL L PWM A Block 54 L H H −PWM A Block 56 H L H −PWM B Block 58 H H L−PWM C Block 60

Referring now to FIG. 4, there is shown a method 70 for triggeringacquisition of phase currents for motor control, according to anembodiment of the present invention. The method 70 may include a step 72of obtaining a PWM signal (e.g., PWM signals 18 a, 18 b, 18 c) from eachphase of the motor control. The method 70 may further include a step 74of inputting each of the PWM signals to a control logic (e.g., AND block30, NOR block 32, blocks 50, 52, 54, 56, 58, 60 or combinationsthereof). For example, when the control logic is an AND block, thecontrol logic may AND together each of the PWM signals. Therefore, theoutput of the control logic (AND gate) is high only when each of the PWMsignals is high. Similarly, when the control logic is a NOR block, theoutput of the control logic (NOR gate) is high only when each of the PWMsignals is low. The method 70 may further include a step 76 oftriggering current acquisition when the control logic generates a highsignal for a predefined valid PWM state. This predefined valid PWM statemay be determined by the use of a mode selector (e.g., mode selector 36)and a multiplexer (e.g., multiplexer 34). The method 70 may furtherinclude a step 78 of creating an edge signal from the high signal,wherein the edge signal is used to trigger an ADC for currentacquisition.

It should be understood, of course, that the foregoing relates toexemplary embodiments of the invention and that modifications may bemade without departing from the spirit and scope of the invention as setforth in the following claims.

1. A trigger mechanism for current acquisition comprising: an invertergenerating pulse width modulation (PWM) signals for each phase of amotor; at least one control logic comparing the PWM signals andgenerating an output signal from at least one of the control logic,wherein when the output signal is high, the output signal is used totrigger current acquisition by an analog to digital converter (ADC). 2.The trigger mechanism of claim 1, wherein the at least one control logiccomprises an AND block and a NOR block, the AND block generating a highoutput signal when each of the PWM signals are in a logic 1 state, andthe NOR block generating a high output signal when each of the PWMsignals are in a logic 0 state.
 3. The trigger mechanism of claim 1,wherein the PWM signals include three PWM signals, one from eachcorresponding phase of the motor.
 4. The trigger mechanism of claim 1,further comprising: a multiplexer receiving the output signal for eachof the at least one control logic; and a mode input for selecting oneoutput signal as an output from the multiplexer.
 5. The triggermechanism of claim 1, further comprising an edge detector receiving theoutput signal and generating an edge signal therefrom, the edge signaltriggering the ADC.
 6. The trigger mechanism of claim 4, furthercomprising an edge detector receiving the output from the multiplexerand generating an edge signal therefrom, the edge signal triggering theADC.
 7. The trigger mechanism of claim 1, wherein the at least onecontrol logic includes a logic block for outputting a high signal whenat least one of the PWM signals are in a logic 1 state and when at leastone of the PWM signals are in a logic 0 state.
 8. The trigger mechanismof claim 7, further comprising: a multiplexer receiving the outputsignal for each of the at least one control logic; and a mode input forselecting one output signal as an output from the multiplexer.
 9. Thetrigger mechanism of claim 7, further comprising an edge detectorreceiving the output signal and generating an edge signal therefrom, theedge signal triggering the ADC.
 10. The trigger mechanism of claim 8,further comprising an edge detector receiving the output from themultiplexer and generating an edge signal therefrom, the edge signaltriggering the ADC.
 11. A trigger mechanism for current acquisitioncomprising: an inverter generating three pulse width modulation (PWM)signals, one PWM signal for each of the three phases of a motor; an ANDblock and a NOR block, each receiving the three PWM signals and eachgenerating an output signal, wherein the AND block generating a highoutput signal when each of the three PWM signals are in a logic 1 state,and the NOR block generating a high output signal when each of the threePWM signals are in a logic 0 state, wherein when the output signal ishigh, the output signal is used to trigger current acquisition by ananalog to digital converter (ADC).
 12. The trigger mechanism of claim 11further comprising: a multiplexer receiving the output signal from theAND block and from the NOR block; a mode input for selecting one outputsignal as an output from the multiplexer; and an edge detector receivingthe output signal from the multiplexer and generating an edge signaltherefrom, the edge signal triggering the ADC when the output signalfrom the multiplexer is high.
 13. The trigger mechanism of claim 11,wherein the trigger mechanic further includes at least one logic blockfor outputting an additional output signal, the additional output signalbeing a high output signal when at least one of the three PWM signalsare in a logic 1 state and when at least one of the three PWM signalsare in a logic 0 state.
 14. The trigger mechanism of claim 13, whereinthe at least one logic block includes six logic blocks, one for eachpossible combination of the three PWM signals wherein at least one ofthe three PWM signals are in a logic 1 state and when at least one ofthe three PWM signals are in a logic 0 state.
 15. A method fortriggering acquisition of phase currents for motor control, the methodcomprising: obtaining a PWM signal from each phase of the motor control;inputting each of the PWM signals to a control logic; and triggeringcurrent acquisition when the control logic generates a high signal for apredefined valid PWM state.
 16. The method of claim 15, furthercomprising defining a valid PWM state as one of a logic 1 state or alogic 0 state.
 17. The method of claim 15, further comprising creatingan edge signal from the high signal, wherein the edge signal is used totrigger an analog to digital converter (ADC) for current acquisition.18. The method of claim 15, further comprising using three phases forthe motor control.